1. Field of the Invention
The present invention relates generally to electronic circuit board structures. The invention also relates to the fabrication and use of circuit boards which are laminated through stacked interconnection. The invention specifically relates to the efficient manufacture and use of stackable circuit board layers, and the use of such circuit board layers in conjunction with board layers providing capacitive structures.
2. Description of Related Art
Fine pitch pattern multilayer printed circuit boards are routinely used to interconnect integrated circuit devices in complex electronic apparatus, including but not limited to computer systems. As the pitch of the conventionally used copper patterns in the various layers of the boards decrease, the layer-to-layer interconnection has proven to be more challenging when accomplished through the conventional practice of drilling and plating vias, including the use of blind vias or plugs.
In such multilayer boards, it is common to use planar sheets of copper as ground paths, as power supply paths and as shields between signal line layers. Integrated circuit packages routinely have decoupling capacitors mounted immediately adjacent their power supply leads, on the surface of the printed circuit board, to reduce noise.
The difficulty of manufacturing multilayer printed circuit boards in the fine wiring pitches needed for direct attach of integrated circuit die, such as exists with the flip-chip technology, led to the use of high density circuit boards or substrates as described in U.S. Pat. No. 5,146,674, the subject matter of which is incorporated by reference herein. The technology characterized by this patent involves the formation of individual layers, for a concluding multilayer board design, from electrically conductive planar sheets. Vias and plugs are formed in dielectrically insulated holes through the sheets. Signal lines are patterned in conductive layers deposited on dielectric layers formed over the metallic core sheet. Vertical interconnections are created through patterns of vias and plugs during the mating of successive layers by aligned compression.
Given that vias and plugs serve similar vertical interconnect functions, use of the term "via" hereafter is intended to encompass both forms of structures.
Reliable connection between the vias is accomplished through dendrites formed on the ends of the vias. The dendrites physically contact corresponding dendrites in other layer vias when the aligned layers are compressed. The formation and use of such dendrites is described in U.S. Pat. No. 5,137,461, the subject matter of which is incorporated by reference herein.
Further refinements in the use of such vertically interconnected board structures are described in U.S. Pat. No. 5,363,275, the subject matter of which is also incorporated by reference herein. This patent focuses on the selective lamination of numerous layers to both interconnect high density flip-chip devices as well as to provide the basic flexible cable resource for interconnecting groupings of such layers as may be used with a modularized component computer system.
Fabrication of the laminar stackable circuit boards which comprise the individual layers of the multilayer interconnect systems sought in the aforementioned U.S. Pat. Nos. 5,146,674 and 5,363,275 depend upon the process in U.S. Pat. No. 5,146,674 to create the individual layers. Though viable, the process is unfortunately complex and therefore costly.
As digital system clock rates and the number integrated circuit die I/O lines increase, capacitive decoupling of the power supply at the leads of the integrated circuit die becomes more important. The prior art practice of mounting decoupling capacitors adjacent the integrated circuit packages is not desirable for a number of reasons. First, the use of such capacitors requires extra fabrication operations. In addition, the capacitors are relatively large in relation to contemporary integrated circuit devices. Lastly, since the capacitors are surface mounted devices, the ground and power supply connections must be routed to the surface at the capacitor leads, introducing resistance and inductance in the decoupling path.
Though capacitive structures may be incorporated into the integrated circuit die, the cost in silicon area and magnitude of capacitance obtainable seldom justify that approach.
Therefore, there remains a need for a process suitable to create the individual layers of an advanced laminar stackable circuit board structure.